Features and Applications Allegro Sigrity
-Perform a wide range of SI analysis or Signal integrity (signal integrity)
-Early detection of design errors to increase success in the early phases
-Restrictions can be set quickly and accurately apply the basic processes
-Improve product performance through exploration and space solutions
-Evaluation of alternative topologies in infancy
-Production of S parameters of the topology and signal analysis in the form of parameter S
-Tables estimate interference designed to increase productivity
-Was approved after PCB design and IC design directly on boards
-Multiple evaluation and confirmation signals for different paths on silicon boards

Sigrity 2021 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis

Interconnect Modeling Technology
-Upgraded interconnect modeling technology addresses latest trends on PCB and IC package design.With signal speeds climbing to 32Gbps and faster, the need to strategically model PCBs and connectors as one structure is now required. The new Cadence® Sigrity™ 3D Workbench, included with the Sigrity PowerSI 3D EM Extraction Option (3DEM), allows users to import mechanical structures, such as cables and connectors, and merge them with the PCB. This way critical 3D structures that cross from the board to the connector can be modeled and optimized as one structure. Updates to the PCB can be automatically back-annotated to the PCB layout tool.

The 3D Workbench offers
-SI and PI applications
-A familiar 3D look and feel
-Ability to import mechanical structures
-Ability to import electrical databases and merge with mechanical structures
-3D solid modeling (parametric and full featured)
-Simulation of
-Twisted pair wiring (cables)
-Backplane plus connectors
-Connector modeling (HDMI, SATA, etc.)
-SMA connector on a PCB

Rigid-Flex Support
Industry-first full Rigid-Flex PCB extraction from a single layout database provides accurate interconnect modeling of both rigid and meshed-ground flex cable zones. The zone information is automatically imported from version 17.2 of Cadence Allegro® technology.

Faster IC Package Modeling
-IC package modeling of designs with thousands of bumps/balls is now 3X faster and memory consumption has been reduced by 75 percent.

Power Integrity Updates
-Upgraded power integrity (PI) technology addresses new checking requirements and new usability requirements for PCB front-to-back design flows. Many enhancements have been added, including hierarchical views, quick search, and filtering, comparison tree report, and tool tips.

Allegro PowerTree™ technology
-The DC analysis technology has been upgraded to support integration with Allegro technology, HTML block-diagram enhancements, and automated add-nodes-on-pads enhancements.

Sigrity PowerDC™ technology
-The AC analysis technology has added some additional checks that now look at the weighted AC current and checks for equal voltage. New batch-mode “projects” allow these two new workflows as well as others to be setup as a set of batch checks.

Sigrity OptimizePI™ technology
-Upgraded signal integrity (SI) technology accelerates the time it takes to verify memory interfaces, serial links, and the plethora of other signals on a PCB that can cause a design to fail in the lab. The technology now features workflows and visions that can be used to quickly perform electrical rule checks that find impedance variations and excessive coupling. These checks require no models and can be run by both expert and non-experts in signal integrity.